Search - fpga ram

[VHDL-FPGA-Verilog] 3ram_ram

Description: 程序实现了FPGA内部RAM之间的数据传输。采用了3片RAM+RAM的结构形式。已通过调试-Procedures to achieve the data transmission between the FPGA internal RAM. Uses 3 RAM+RAM structure. Has passed through debugging
Platform: | Size: 28584960 | Author: 袁官福 | Hits:

[VHDL-FPGA-Verilog] ram_fpgavhdl

Description: fpga vhdl实现一个标准双端口ram，可以作为单端口或者双端口用 -fpga vhdl achieve a standard dual-port ram, can be used as a single port or dual port with a
Platform: | Size: 3072 | Author: 站长 | Hits:

[VHDL-FPGA-Verilog] m4k-example

Description: FPGA中M4K的使用例子，比如rom ram-the example to useing M4K in FPGA
Platform: | Size: 1711104 | Author: fu | Hits:

[VHDL-FPGA-Verilog] PseudoHC11_MCU

Description: This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.
Platform: | Size: 12288 | Author: mahedros87 | Hits:

[VHDL-FPGA-Verilog] ygyTest

Description: 利用开源网站上的8051核，在Spartan 3A开发板上实现成功，开发环境是Xilinx ISE Design Suite 12.3，顶层文件基于原理图开发，扩展了外部ROM和RAM，且更改了地址宽度-implment the mc8051 IP in spartan-3A FPGA starten kit.
Platform: | Size: 18179072 | Author: 杜春城 | Hits:

[VHDL-FPGA-Verilog] spram

Description: 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
Platform: | Size: 2859008 | Author: | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用FPGA实现了CPU中RAM,ROM等功能，设计比较完整-FPGA Implementation of a CPU, RAM, ROM, function, design is more complete
Platform: | Size: 1270784 | Author: shenhaoxing | Hits:

[VHDL-FPGA-Verilog] Port-RAMs

Description: 介绍双口ram功能，进一步了解在fpga上怎么设计一个双口ram-Introduced the dual-port ram function to learn more about the fpga on how to design a dual port ram
Platform: | Size: 352256 | Author: 吴越强 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FPGA内设计同步FIFO和异步FIFO，以及双口RAM的方法,FIFO设计的经验之谈，非常经典。-Synchronous FIFO and asynchronous FIFO, and dual-port RAM within the FPGA design,FIFO design rule of thumb, very classic.
Platform: | Size: 2388992 | Author: peter | Hits:

[VHDL-FPGA-Verilog] ActelFPGA_RAM_an

Description: FPGA下开发RAM的手册，与FPGA自带的说明不同-FPGA development manual of RAM, comes with instructions and FPGA
Platform: | Size: 271360 | Author: tanjl | Hits:

[Industry research] test

Description: The design shows how to use Dual port RAM in FPGA design
Platform: | Size: 1024 | Author: Rohit Mahajan | Hits:

[VHDL-FPGA-Verilog] jpeg_hardware.tar

Description: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co
Platform: | Size: 868352 | Author: | Hits:

[VHDL-FPGA-Verilog] verilog--sram

Description: ram的fpga应用，用verilog语言实现，适用于cyclone 2系列-ram the fpga application verilog language applicable to cyclone 2
Platform: | Size: 96256 | Author: sunlin | Hits:

[VHDL-FPGA-Verilog] caiji1

Description: 利用两个双口ram做的乒乓操作，采集高速大容量数据，fpga写，arm读-Two dual-port ram to do the ping-pong operation, collecting high-speed large-capacity data, fpga write, arm reading
Platform: | Size: 6946816 | Author: 李遥 | Hits:

[Other] read_wirte_ram

Description: FPGA实现双口RAM功能，从而用FPGA实现双控制器间的数据交换-FPGA realization of dual-port RAM functions, the exchange of data between the dual-controller with FPGA
Platform: | Size: 1024 | Author: | Hits:

[Software Engineering] 256X16RAM

Description: FPGA硬件中控制RAM存储，使用256x16的RAM-FPGA hardware to control the RAM memory, 256x16 of RAM
Platform: | Size: 2048 | Author: 苏亭 | Hits:

[Industry research] Using-the-Virtex-Block-SelectRAMP

Description: The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, or a write port, and each port can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs.-The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, or a write port, and each port can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs.
Platform: | Size: 66560 | Author: asura | Hits:

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